74HC573 - Octal D-type Transparent Latch IC
The HC573 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Old data can be retained, or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The latch is the use of the level control input data, without including the latch and with a controllable latch enable control.
Specifications
- Supply Voltage Range: 0.7 to 7V
- Max supply current: 50mA
- Continuous drain current: 35mA
- Storage Temperature Range: -65ᵒC to 150ᵒC
- Max transition time: 1000ns
Product Description
Here LE means Latch Input pin, when LE is high, the Output Pins(Q) will follow the Data input Pins(D), puts. When LE is low, the Q outputs are latched at the logic levels of the D. You need to power the IC with VCC and GND pins
Additional Resources
Package Contents
1×74HC573 - Octal D-type Transparent Latch IC
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74HC573 - Octal D-type Transparent Latch IC
The HC573 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Old data can be retained, or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The latch is the use of the level control input data, without including the latch and with a controllable latch enable control.
Specifications
- Supply Voltage Range: 0.7 to 7V
- Max supply current: 50mA
- Continuous drain current: 35mA
- Storage Temperature Range: -65ᵒC to 150ᵒC
- Max transition time: 1000ns
Product Description
Here LE means Latch Input pin, when LE is high, the Output Pins(Q) will follow the Data input Pins(D), puts. When LE is low, the Q outputs are latched at the logic levels of the D. You need to power the IC with VCC and GND pins
Additional Resources
Package Contents
1×74HC573 - Octal D-type Transparent Latch IC
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Product Information
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Description
The HC573 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Old data can be retained, or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The latch is the use of the level control input data, without including the latch and with a controllable latch enable control.
Specifications
- Supply Voltage Range: 0.7 to 7V
- Max supply current: 50mA
- Continuous drain current: 35mA
- Storage Temperature Range: -65ᵒC to 150ᵒC
- Max transition time: 1000ns
Product Description
Here LE means Latch Input pin, when LE is high, the Output Pins(Q) will follow the Data input Pins(D), puts. When LE is low, the Q outputs are latched at the logic levels of the D. You need to power the IC with VCC and GND pins
Additional Resources
Package Contents
1×74HC573 - Octal D-type Transparent Latch IC
